Let AI see
what cameras were never built to show.
Semantic chip architecture for AI cameras.
Cameras were built to make pictures for people. PixelASIC is developing a camera-side semantic chip that extracts machine-useful features from the raw sensor stream — before human-oriented processing and compression can suppress the cues that downstream AI depends on. Designed to deliver cleaner machine evidence at lower bandwidth, compute load, and power.
Starting where the advantage is largest: distant drone detection.
AI vision still starts with too many pixels.
Camera pipelines were designed to produce good-looking video for human viewers. Downstream AI models need something different: compact perception evidence such as motion, regions, features, object cues, and metadata — and conventional processing can suppress exactly those cues. Most cameras still stream full human-oriented image data.
PixelASIC moves part of the perception pipeline closer to the sensor.
As an engineering example: an IMX530-class 24.5 MP sensor at PixelASIC's operating point produces approximately 24–26 Gbit/s of raw data per camera.
From pixel streams to semantic streams.
The PixelASIC architecture is designed to send compact machine-useful information instead of always sending full pixel streams. The chip is designed to extract weak detection cues earlier in the camera pipeline, before conventional image processing and compression can suppress them.
What is different
PixelASIC is not building a complete camera, event sensor, generic edge-AI box, or video codec. The company is developing a camera-side semantic chip for conventional frame sensors, using streaming line-based processing designed to extract weak machine-useful cues close to the image sensor, before conventional ISP and compression can suppress them. The goal is to provide downstream AI systems with cleaner semantic input, not to replace the AI model.
Built for scalable AI-camera systems.
The architecture is designed to deliver:
Cleaner machine evidence for downstream AI — strongest for small, low-contrast targets.
Lower bandwidth from sensor to host.
Lower compute load on the downstream AI system.
Lower power for camera-side perception.
Faster perception for latency-sensitive systems.
Better scaling for distributed AI cameras.
Industry standards are moving in the same direction
MPEG is developing Video Coding for Machines (VCM) and Feature Coding for Machines (FCM), standards for coding visual data and intermediate neural-network features for machine analysis. FCM reached Committee Draft in May 2026 and remains under development. It defines a feature bitstream and decoding process for split inference; it does not define the raw image-sensor interface, region selection, sensor control, or camera-side hardware.
This validates a direction PixelASIC shares: AI systems will increasingly exchange machine-oriented evidence, not only human-viewable video. For compatible split-model deployments, a future PixelASIC feature-output mode could target FCM compatibility. FCM is a potential interface standard — not PixelASIC's moat. PixelASIC's differentiation is the sensor-side architecture designed to generate compact machine evidence directly from the raw sensor stream.
Starting with distant drone detection.
Small drones are difficult AI-camera targets: distant, low contrast, fast moving, and often only a few pixels wide. Conventional video pipelines can make the image look cleaner while making the machine signal weaker.
Software model → FPGA demonstrator → semantic sensor-node ASIC.
PixelASIC is currently in pre-silicon R&D. The development path starts with software validation, continues to an FPGA demonstrator, and targets a camera-side semantic ASIC.
M1 — Measurement and validation
Capture raw sensor data, validate feature-selection methods, and establish quantitative targets.
FPGA demonstrator
Validate real-time streaming ingest, processing, sensor control, and semantic output.
Semantic Sensor-Node ASIC
Dedicated low-power production silicon.
// Timelines are indicative and depend on funding, technical validation, partner engagement, and foundry or implementation access.
Israeli deep-tech venture
PixelASIC combines semiconductor architecture, embedded systems, machine perception, and AI sensing.
Seeking image-sensor, FPGA, semiconductor implementation, defense-sensing, and design-partner collaborations.
Patent-pending technology covering camera-side semantic preprocessing, feature extraction, compact semantic streams, and AI-camera architectures.